posted on Dec, 1 2004 @ 02:10 AM
I'm amazed nobody has reported this already of this insanely great product due out sometime in 2006.
Sony, IBM and Toshiba have revealed that they will be formally explaining the Cell chip at the International Solid State Circuits Conference (ISSCC)
on the 6th Feb 2005.
IBM and Sony also said they are now ready to announce the promised Cell-based workstation, which should enable software developers to begin coding for
the PlayStation 3, itself set to be based on the new chip.
The trio described Cell as a 64-bit POWER-based "multi-core system" for computers and next-generation digital home appliances. Crucially, each core
can run a single operating system, or run their own OS independently of the others.
The chip's makers note that Cell is not only a multi-core architecture - like the anticipated 'Antares' PowerPC 970MP - but multi-threaded too,
though it's not yet clear whether support for multiple threads takes places within each core level, Hyper Threading-style, or by spreading threads
across cores. IBM's POWER 5 architecture supports simultaneous multi-threading, so it seems likely Cell will too.
IBM and Sony also talk about big memory and I/O bandwidth - no great surprise there, given it's a 64-bit processor and what IBM has demonstrated with
existing POWER and PowerPC processors. More interesting is the integration of a security sub-system. The companies don't go into any detail, but it
sounds not unlike VIA's PadLock technology with its hardware random number generator. Mention is made of "high-level media processing", which could
be a reference to AltiVec, the PowerPC SIMD engine.
There's also the suggestion that Cell will use a SpeedStep-style power conservation technology, allowing the chip to reduced its clock frequency.
IBM's 90nm PowerPC 970 already has something along these lines.
Also, contrary to past speculation that Cell would ship at 65nm, its makers today said it will debut as a 90nm part using IBM's SOI technology.
The Chip is set to feature in Sony’s PlayStation 3 console, but the architecture also addresses many other applications such as set-top boxes and
> The processor leverages a multicore 64-bit Power architecture with an embedded streaming processor, high-speed I/O, SRAM and dynamic multiplier.
> The Cell architecture rests on two concepts: the "apulet," a bundle comprising a data object and the code necessary to perform an action upon it;
and the "processing element," a hierarchical bundle of control and streaming processor resources that can execute any apulet at any time. The
apulets appear to be completely portable among the processing elements in a system, so that tasks can be doled out dynamically by assigning a waiting
apulet to an available processing element.
> Giving scale to the performance targets for the project, one of the ISSCC papers puts the performance of the streaming-processor SRAM at 4.8 GHz.
This suggests the data transfer rate for 128-bit words across the local bus within the processing element.
> Each processing element comprises a Power-architecture 64-bit RISC CPU, a highly sophisticated direct-memory access controller and up to eight
identical streaming processors.